Supported hardware - Top - Midas build options and operation considerations 
Midas defines its own set of CAMAC, VME and FASTBUS calls in order to unify the different hardware modules that it supports. This interface method permits to be totally hardware as well as OS independent. The same user code developed on a system can be used as a template for another application on a different operating system.
While the file mcstd.h (Midas Camac Standard) provides the interface for the CAMAC access, the file mvmestd.h (Midas VME Standard) is for the VME access. An extra CAMAC interface built on the top of mcstd provides the ESONE standard CAMAC calls (esone.c).
Refers to the corresponding directories under /drivers to find out what module of each family is already supported by the current Midas distribution. /drivers/divers contains older drivers which has not yet been converted to the latest API.
Please refer to esone.c for function description.
The output of this latch is shaped (limited in its pulse with to match the ADC gate width) and distributed to the ADC's. This scheme has two problems. The computer generates the reset signal, usually by two CAMAC output functions to a CAMAC IO unit. Therefore the duration of the pulse is a couple of ms. There is a non-negligible probability that during the reset pulse there is another hardware trigger. If this happens and both inputs of the latch are active, its function is undefined. Usually it generates several output pulses that lead to wrong ADC values. The second problem lies in the fact that the latch can be just reset when a trigger input is active. This can happen since trigger signals usually have a width of a few tens of nanoseconds. In this case the latch output signal does not carry the timing of the trigger signal, but the timing of the reset signal. The wrong timing of the output can lead to false ADC and TDC signals. To overcome this problem, a more elaborate scheme is necessary. One possible solution is the use of a latch module with edge-sensitive input and veto input. At PSI, the module "D. TRIGGER / DT102" can be used. The veto input is also connected to the computer:
To reset this latch, following bit sequence is applied to the computer output (signals are displayed active low):
The active veto signal during the reset pulse avoids that the latch can receive a "set" and a "reset" simultaneously. The edge sensitive input ensures that the latch can only trigger on a leading edge of a trigger signal, not on the removing of the veto signal. This ensures that the timing of the trigger is always carried at the ADC/TDC gate signal.
Supported hardware - Top - Midas build options and operation considerations