Low-Energy Muon (LEM) Experiment  0.5.2
v1190.h
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1 /********************************************************************\
2 
3  Name: v1190.h
4  Created by: Thomas Prokscha
5 
6  Cotents: Header file for CAEN VME V1190 TDC.
7 
8  $Id$
9 
10 \********************************************************************/
11 
12 typedef struct {
13  DWORD data:19;
14  WORD channel:7;
15  WORD edge:1;
16  WORD buffer:3;
17  WORD filler:2;
18 } V1190_DATA;
19 
20 #define V1190_DATA_MASK 0x0007FFFF
21 #define V1190_CHANNEL_MASK 0x01F80000
22 #define V1190_EDGE_MASK 0x02000000
23 #define V1190_ERROR_BIT_MASK 0x20000000
24 #define V1190_ERROR_TDC_MASK 0x03000000
25 #define V1190_ERROR_FLAG_MASK 0x00007FFF
26 
27 #define V1190_OUTPUT_BUFFER_SIZE 32768
28 
29 /* Module addresses */
30 #define V1190_OUTPUT_BUFFER 0x0000
31 #define V1190_CONTROL_REGISTER 0x1000
32 #define V1190_STATUS_REGISTER 0x1002
33 #define V1190_INTERRUPT_LEVEL 0x100A
34 #define V1190_INTERRUPT_VECTOR 0x100C
35 #define V1190_GEO_ADDRESS 0x100E
36 #define V1190_MCST_BASE_ADDRESS 0x1010
37 #define V1190_MCST_CBLT_CTRL 0x1012
38 
39 #define V1190_MODULE_RESET 0x1014
40 #define V1190_SOFTWARE_CLEAR 0x1016
41 #define V1190_SOFTWARE_EVENT_RESET 0x1018
42 #define V1190_SOFTWARE_TRIGGER 0x101A
43 #define V1190_EVENT_COUNTER 0x101C
44 #define V1190_EVENT_STORED 0x1020
45 #define V1190_ALMOST_FULL_LEVEL 0x1022
46 #define V1190_BLT_EVENT_NUMBER 0x1024
47 
48 #define V1190_FIRMWARE_REVISION 0x1026
49 #define V1190_TESTREG 0x1028
50 #define V1190_OUT_PROG_CONTROL 0x102C
51 #define V1190_OPCODE_ADDRESS 0x102E
52 #define V1190_MICRO_HANDSHAKE 0x1030
53 #define V1190_SEL_FLASH 0x1032
54 #define V1190_FLASH 0x1034
55 #define V1190_COMPENSATION_SRAM 0x1036
56 #define V1190_EVENT_FIFO 0x1038
57 #define V1190_EVENT_FIFO_STORED 0x103C
58 #define V1190_EVENT_FIFO_STATUS 0x103E
59 #define V1190_DUMMY32 0x1200
60 #define V1190_DUMMY16 0x1204
61 
62 /* Acquisition mode */
63 #define V1190_TRG_MATCH 0x0000
64 #define V1190_CONT_STOR 0x0100
65 #define V1190_READ_ACQ_MOD 0x0200
66 #define V1190_SET_KEEP_TOKEN 0x0300
67 #define V1190_CLEAR_KEEP_TOKEN 0x0400
68 #define V1190_LOAD_DEF_CONFIG 0x0500
69 #define V1190_SAVE_USER_CONFIG 0x0600
70 #define V1190_LOAD_USER_CONFIG 0x0700
71 #define V1190_AUTOLOAD_USER_CONFIG 0x0800
72 #define V1190_AUTOLOAD_DEF_CONFIG 0x0900
73 
74 /* Trigger */
75 #define V1190_SET_WIN_WIDTH 0x1000
76 #define V1190_SET_WIN_OFFS 0x1100
77 #define V1190_SET_SW_MARGIN 0x1200
78 #define V1190_SET_REJ_MARGIN 0x1300
79 #define V1190_EN_SUB_TRG 0x1400
80 #define V1190_DIS_SUB_TRG 0x1500
81 #define V1190_READ_TRG_CONF 0x1600
82 
83 /* TDC edge detection and resolution */
84 #define V1190_SET_DETECTION 0x2200
85 #define V1190_READ_DETECTION 0x2300
86 #define V1190_SET_TR_LEAD_LSB 0x2400
87 #define V1190_SET_PAIR_RES 0x2500
88 #define V1190_READ_RES 0x2600
89 #define V1190_SET_DEAD_TIME 0x2800
90 #define V1190_READ_DEAD_TIME 0x2900
91 
92 /* TDC readout */
93 #define V1190_ENABLE_HEADER 0x3000
94 #define V1190_DISABLE_HEADER 0x3100
95 #define V1190_READ_HEADER 0x3200
96 #define V1190_SET_EVENT_SIZE 0x3300
97 #define V1190_READ_EVENT_SIZE 0x3400
98 #define V1190_ENABLE_ERROR_MARK 0x3500
99 #define V1190_DISABLE_ERROR_MARK 0x3600
100 #define V1190_ENABLE_ERROR_BYPASS 0x3700
101 #define V1190_DISABLE_ERROR_BYPASS 0x3800
102 #define V1190_SET_ERROR_TYPES 0x3900
103 #define V1190_READ_ERROR_TYPES 0x3A00
104 #define V1190_SET_FIFO_SIZE 0x3B00
105 #define V1190_READ_FIFO_SIZE 0x3C00
106 
107 /* Channel enable */
108 #define V1190_ENABLE_CHANNEL 0x4000 /* 40nn enable channel nn */
109 #define V1190_DISABLE_CHANNEL 0x4100 /* 41nn disable channel nn */
110 #define V1190_ENABLE_ALL_CHANNEL 0x4200
111 #define V1190_DISABLE_ALL_CHANNEL 0x4300
112 #define V1190_WRITE_ENABLE_PATTERN 0x4400
113 #define V1190_READ_ENABLE_PATTERN 0x4500
114 #define V1190_WRITE_ENABLE_PATTERN32 0x4600
115 #define V1190_READ_ENABLE_PATTERN32 0x4700
116 
117 /* adjust */
118 #define V1190_SET_GLOB_OFFS 0x5000
119 #define V1190_READ_GLOB_OFSS 0x5100
120 #define V1190_SET_ADJUST_CHANNEL 0x5200 /* 52nn set channel nn adjust */
121 #define V1190_READ_ADJUST_CHANNEL 0x5300 /* 53nn read channel nn adjust */
122 #define V1190_SET_RC_ADJ 0x5400 /* 540n set rc adjust of tdc 0n */
123 #define V1190_READ_RC_ADJ 0x5500 /* 550n */
124 #define V1190_SAVE_RC_ADJ 0x5600 /* 560n */
125 
126 /* misceallanous */
127 #define V1190_READ_TDC_ID 0x6000 /* 600n read programmed ID of TDC 0n */
128 #define V1190_READ_MICRO_REV 0x6100 /* read firmware revision of micro controller */
129 #define V1190_RESET_DLL_PLL 0x6200
130 
131 /* Advanced */
132 #define V1190_WRITE_SETUP_REG 0x7000 /* 70nn */
133 #define V1190_READ_SETUP_REG 0x7100 /* 71nn */
134 #define V1190_UPDATE_SETUP_REG 0x7200
135 #define V1190_DEFAULT_SETUP_REG 0x7300
136 #define V1190_READ_ERROR_STATUS 0x7400 /* 740n read error status of TDC n*/
137 #define V1190_READ_DLL_LOCK 0x7500 /* 750n DLL lock bit of TDC n */
138 #define V1190_READ_STATUS_STREAM 0x7600 /* 760n read TDC n status */
139 #define V1190_UPDATE_SETUP_TDC 0x7700 /* 770n setup on TDC n */
140 
141 /* Debug and test */
142 #define V1190_WRITE_EEPROM 0xC000 /* write 1 byte into EEPROM */
143 #define V1190_READ_EEPROM 0xC100 /* read 1 byte */
144 #define V1190_REVISION_MICRO_CONTROLLER 0xC200
145 #define V1190_WRITE_SPARE 0xC300
146 #define V1190_READ_SPARE 0xC400
147 #define V1190_ENABLE_TEST_MODE 0xC500
148 #define V1190_DISABLE_TEST_MODE 0xC600
149 #define V1190_SET_TDC_TEST_OUTPUT 0xC700 /* C70n set TDC n signal test output */
150 #define V1190_SET_DLL_CLOCK 0xC800
151 #define V1190_READ_TDC_SETUP_SCAN_PATH 0xC900 /* C90n for TDC n */
152 
153 /*-----------------------------------------------------------------------*/
154 #define V1190_TRG_MATCH_MASK 0x01
155 #define V1190_CONT_STOR_MASK 0x00
156 
157 #define V1190_EDGE_PAIR_MODE 0x00
158 #define V1190_EDGE_TRAILING_MODE 0x01
159 #define V1190_EDGE_LEADING_MODE 0x02
160 #define V1190_EDGE_TRAILING_LEADING_MODE 0x03
161 
162 #define V1190_LSB_800PS 0x00
163 #define V1190_LSB_200PS 0x01
164 #define V1190_LSB_100PS 0x02 /* default */
165 
166 #define V1190_DEAD_TIME_5NS 0x00 /* default */
167 #define V1190_DEAD_TIME_10NS 0x01
168 #define V1190_DEAD_TIME_30NS 0x02
169 #define V1190_DEAD_TIME_100NS 0x03
170 
171 #define V1190_HEADER_DISABLED 0x00
172 #define V1190_HEADER_ENABLED 0x01
173 
174 #define V1190_MAX_EVENTS_0 0x0000
175 #define V1190_MAX_EVENTS_1 0x0001
176 #define V1190_MAX_EVENTS_2 0x0002
177 #define V1190_MAX_EVENTS_4 0x0003
178 #define V1190_MAX_EVENTS_8 0x0004
179 #define V1190_MAX_EVENTS_16 0x0005
180 #define V1190_MAX_EVENTS_32 0x0006
181 #define V1190_MAX_EVENTS_64 0x0007
182 #define V1190_MAX_EVENTS_128 0x0008
183 #define V1190_MAX_EVENTS_NOLIMIT 0x0009 /* default */
184 
185 /* readout mode */
186 #define A32D32 0
187 #define A32BLT32 1
188 #define A32MBLT64 2
189 #define A32_2eVME 3
190 
191 /* status register bits */
192 #define V1190_DATAREADY_BIT 0x0001
193 #define V1190_ALMFULL_BIT 0x0002
194 #define V1190_FULL_BIT 0x0004
195 
196